1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display (LCD) device and a method of manufacturing the same.
2. Discussion of the Related Art
Until recently, display devices have typically used cathode-ray tubes (CRTs). Presently, many efforts and studies are being made to develop various types of flat panel displays, such as liquid crystal display (LCD) devices, plasma display panels (PDPs), field emission displays, and electro-luminescence displays (ELDs), as a substitute for CRTs. Of these flat panel displays, LCD devices have many advantages, such as high resolution, light weight, thin profile, compact size, and low voltage power supply requirements.
In general, an LCD device includes two substrates that are spaced apart and face each other with a liquid crystal material interposed between the two substrates. The two substrates include electrodes that face each other such that a voltage applied between the electrodes induces an electric field across the liquid crystal material. Alignment of the liquid crystal molecules in the liquid crystal material changes in accordance with the intensity of the induced electric field into the direction of the induced electric field, thereby changing the light transmissivity of the LCD device. Thus, the LCD device displays images by varying the intensity of the induced electric field.
FIG. 1 is a cross-sectional view illustrating an array substrate for an LCD device according to the related art.
FIG. 1 shows the array substrate manufactured through four mask processes. Referring to FIG. 1, the array substrate includes a thin film transistor in a switching region TrA and a data pad in a data pad region DPA on a substrate 10.
The thin film transistor includes a gate electrode 21, a first semiconductor layer 25 and source and drain electrodes 27 and 29. The first semiconductor layer 25 includes an active layer 25a made of intrinsic amorphous silicon and an ohmic contact layer 25b made of impurity-doped amorphous silicon.
A gate insulating layer 23 is on the gate electrode 21. A passivation layer 31 is on the source and drain electrodes 27 and 29 and has a drain contact hole 35 exposing the drain electrode 29. A pixel electrode 33 is connected to the drain electrode 29 through the drain contact hole 35.
In the data pad region DPA, a data pad electrode 41 and a data pad electrode terminal 45 are formed. The data pad electrode 41 is on a second semiconductor layer 26. The second semiconductor layer 26 includes a first pattern 26a made of intrinsic amorphous silicon and a second pattern 26b made of impurity-doped amorphous silicon. The data pad electrode terminal 45 is connected to the data pad electrode 41 through a data pad contact hole 43 of the passivation layer 31.
The data pad electrode 41 is made of molybdenum (Mo) having a low resistance. When the passivation layer 31 is patterned, the data pad electrode 41 of the molybdenum is etched and includes the data pad contact hole 43 therein together with the passivation layer 31. Accordingly, the data pad contact hole 43 exposes a top surface of the second pattern 26b and further exposes inner side surfaces of the data pad electrode 41 surrounding the data pad contact hole 43. This type of contact may be referred to as a side contact.
The data pad contact hole 43 has a rectangular shape in plane. Accordingly, when the data pad electrode terminal 45 has the side contact with the data pad electrode 41, a contact area therebetween is small, and a contact resistance increases. The increase of the contact resistance causes delay of a data signal, and display quality is thus degraded.